1. Field of the Invention
The invention relates to the field of vertically stacked field programmable non-volatile memories and more specifically to methods of fabricating memory arrays utilizing a hard mask.
2. Discussion of Related Art
Recently there has been an interest in fabricating memories having memory cells disposed at numerous levels above a substrate. Each level includes a plurality of spaced-apart first lines extending in one direction which are vertically separated from a plurality of parallel spaced-apart second lines extending perpendicular to the first line. Cells are disposed between the first lines and second lines at the intersections of these lines. These memories are described in U.S. Pat. Nos. 5,835,396 and 6,034,882. Unfortunately, during the fabrication of the lines during the planarization of a gap fill dielectric between the lines, the lines can become eroded which detrimentally effects the reliability and performance of the fabricated memory array.
The present invention is a method of fabricating a semiconductor array. According to the present invention, a semiconductor layer having an upper surface is formed. A masking layer is then formed on the semiconductor layer. The masking layer is then patterned. The semiconductor layer is etched in alignment with the patterned masking layer to define memory array features. The gap between the features is filled with the dielectric material which is softer than the masking layer with respect to a planarization step. The dielectric material is then planarized with the masking layer acting as a polish stop.